This invention relates to an electron beam lithographic microfabrication technology which can be applied to the fabrication of electronic microcircuit devices, for example, such as an LSI (Large Scale Integrated Circuit) or VLSI (Very Large Scale Integrated Circuit). More specifically, this invention relates to a method of electron beam exposure for directly writing patterns on a semiconductor wafer with an electron beam and, particularly, to a method for aligning of an exposure field on a wafer with an electron beam.
For increasing the degree of integration of an LSI, a technique has been developed to form minute and precise patterns using an electron beam exposure method. Among the variety of electron beam exposure methods, a direct exposure method adapted to directly write patterns on chips of a semiconductor wafer makes it possible to form very accurate patterns, and, accordingly, this method has been extensively used for the formation of electrically conductive wiring layers or the like.
In conventional photolithography using an ultraviolet ray exposure, a patterning mask is aligned with the wafer relying on alignment marks, and the accuracy of the mask alignment affects greatly the accuracy of the pattern. However, the electron beam direct exposure method requires a far higher accuracy of alignment of the exposure field on the wafer.
There is a conventional direct exposure method, in which a single exposure field is equivalent to one chip, wherein four rectangular marks, for example, are formed in the peripheral region of the chip, and the chip is brought into alignment with the electron beam by scanning the marks in the peripheral region and correcting the scanning field of the electron beam accordingly, and thereafter the chip is exposed to the electron beam for writing the pattern. Adjusting the alignment for each of the chips ensures a high accuracy of alignment. In recent years, however, there has been a tendency for semiconductor chips (used for memory devices, for example) to be made larger in size. In this case, the exposure field is made larger in size, and the scan field of the electron beam is also, correspondingly, made larger. Therefore, the area which is equivalent to a single bit in a D/A (digital-to-analogue) converter for beam control is increased, and, accordingly, the accuracy of alignment is decreased. Furthermore, there exists a problem in that a chip having a very large size cannot be scanned by the existing electron beam exposure system. For example, to ensure a pattern accuracy of within 0.2 .mu.m, the exposure field should usually be about 2 mm.times.2 mm. If the field is 5 mm.times.5 mm, the alignment accuracy is decreased remarkably, and if the field size is larger than 5 mm.times.5 mm, it is difficult to scan the exposure field with the electron beam at all.
In another conventional method, three or more marks are formed in the peripheral region of the semiconductor wafer, and the alignment of the exposure field with the electron beam is periodically adjusted relying on the marks during the scanning process for exposure. According to this method, however, errors in alignment which stem from deformations, curvature or irregularities of the wafer cannot be corrected, and, accordingly, the alignment accuracy is not very high.